As digital processing technologies expand, it is important for digital down-conversion systems to be well designed. COrdinate Rotation Digital Computer (CORDIC) algorithms avoid direct sine/cosine synthesis and multipliers that are commonly found in digital down-conversion systems.
The CORDIC algorithm is an iterative method to calculate transcendental functions and/or rotate vectors. For the purposes of digital down-conversion, CORDIC algorithms typically rotate an in-phase/quadrature (I/Q) vector at an infrared (IF) frequency and effectively down-convert to a baseband I/Q vector. After an initial ±90 degree rotation, Equations 1-3 are repeatedly used to rotate a vector by a desired amount.
                                          X            i                    +          1                =                              X            i                    -                                    d              i                        ⁡                          (                                                Y                  i                                                  2                  i                                            )                                                          [                  Eqn          .                                          ⁢          1                ]                                                      Y            i                    +          1                =                              Y            i                    -                                    d              i                        ⁡                          (                                                X                  i                                                  2                  i                                            )                                                          [                  Eqn          .                                          ⁢          2                ]                                                      Z            i                    +          1                =                              Z            i                    -                                    d              i                        ⁡                          (                              arctan                ⁢                                  1                                      2                    i                                                              )                                                          [                  Eqn          .                                          ⁢          3                ]            
For Equations 1-3, X is the in-phase portion of the vector (I), Y is the quadrature portion of the vector (Q), and Z is the desired rotation angle. The value “i” is based on the number of required iterations. For Equations 1-3, di=−1 for Zi<0, else di=+1. As the number of iterations increases, the error in the rotation approximation decreases.
Typically, wireless applications require between twelve (12) and sixteen (16) iteration counts to meet performance requirements. In other words, for each I/Q sample, the down-converter uses Equations 1-3 approximately 12 to 16 times. Although this mechanism is more efficient than look up tables and multipliers, the large number of iterations consumes excessive silicon and/or requires significantly faster clock rates.
CORDIC processor implementations essentially focus on using a single piece of hardware iteratively to calculate all 16 iterations or on unrolling the loop and implementing each iteration as a piece of hardware. In single hardware blocks, the minimum clock rate required is the number of iterations multiplied by the data path sample rate.
For wireless applications where performance requirements demand finer precision and a greater number of iterations, the required clock rate is detrimental to power consumption and larger power consuming buffers are often required. For example, if the sample rate of the receiver is 25 MHz, then the required clock rate to down-convert with 16 iterations would be 400 MHz. Even with some of the extreme process nodes, 400 MHz can be a challenging requirement and ultimately unachievable. Moreover, an unrolled version of a CORDIC processor utilizes a hardware stage for each iteration of the algorithm. The area required for down-conversion increases the allotted die area and increases cost.
Therefore, what is needed is an improved CORDIC processor for use in wireless applications.